There are two types of digital filters: IIR (infinite impulse response) filters with an infinite length of impulse response and FIR (finite impulse response) filters with a finite length response. Usually, all of the analog filters may be converted to IIR filters. Compared with FIR filters, IIR filters display a steep cut-off characteristic curve.
FIG. 15 shows the direct-type configuration of a second order IIR filter. This IIR filter comprising of four adders 301, 302, 303, 304, five multipliers 305, 306, 307, 308, 309, and two delay registers 310, 311. One of the input terminals of adder 301 is connected to signal input terminal 300, the other input terminal is connected to the output terminal of adder 302. The output terminal of adder 301 is connected to the input terminal of multiplier 305 and the input terminal of delay means 310. The output terminal of multiplier 305 is connected to one of the input terminals of adder 303. The output terminal of adder 304 is connected to the other input terminal of adder 303, and the output terminal of adder 303 is connected to signal output terminal 312. The output terminal of delay register 310 is connected to the input terminal of multiplier 306, the input terminal of multiplier 308, and the input terminal of delay register 311. The output terminal of delay register 311 is connected to the input terminal of multiplier 307 and the input terminal of multiplier 309. One of the input terminals of adder 302 is connected to the output terminal of multiplier 306. The other input terminal is connected to the output terminal of multiplier 307. One of the input terminals of adder 304 is connected to the output terminal of multiplier 308. The other input terminal is connected to the output terminal of multiplier 309.
Adder 301 adds input signal x(n) and the output of adder 302 and outputs the result. Multiplier 305 multiplies the output of adder 301 by coefficient b.sub.0 and outputs the result. Adder 303 adds the output of multiplier 305 and the output of adder 304 and outputs the output signal y(n). Delay register 310 gives a prescribed delay time to the output of adder 301 and then outputs the result signal; delay register 311 gives a delay time to the output of delay register 310 and outputs the result signal. Multiplier 306 and multiplier 308 multiply the output of delay register 311 by coefficients a.sub.1 and b.sub.1, respectively, and output the result signals, respectively. Multiplier 307 and multiplier 309 multiply the output of delay register 311 by coefficients a.sub.2 and b.sub.2, respectively, and output the result signals. Adder 302 adds the output of multiplier 306 and the output of multiplier 307, and outputs the result signal. Adder 304 adds the output of multiplier 308 and multiplier 309, and outputs the result signal.
The frequency characteristics of the IIR filter depend on the coefficients of the various multipliers, a.sub.1, a.sub.2, b.sub.o, b.sub.1, and b.sub.2. Signal x(n) input into adder 301 is processed by filtering corresponding to the aforementioned frequency characteristics, and output signal y(n) is output from adder 303.
In this type of IIR filter, in order to further steepen the frequency characteristics, it is necessary to increase the order of the filter used. For example, if the order of the second order IIR filter shown in FIG. 15 is increased to a third IIR filter, the configuration becomes that shown in FIG. 16. If the order is further increased, the Nth IIR filter has a configuration shown in FIG. 17.
For the third IIR filter shown in FIG. 16, the configuration is formed by adding two adders 313, 314, one delay register 315 and two multipliers 316, 317 in ladder form to the second order filter shown in FIG. 15. That is, adder 313 is inserted between multiplier 307 and adder 302, adder 314 is inserted between multiplier 309 and adder 304, delay register 315 is connected to the connection point between delay register 311 and multipliers 307, 309, multiplier 316 is connected between delay register 315 and adder 313, and multiplier 317 is connected between delay register 315 and adder 314.
Similarly, the Nth IIR filter shown in FIG. 17 is formed by adding 2N-4 adders, N-2 delay registers, and 2N-4 multipliers to the second order IIR filter shown in FIG. 15. In this way, for the direct-type IIR filter, each time when the order of the filter is increased by one, one delay register, two multipliers, and two adders are added in ladder form.
In the aforementioned direct-type IIR filter, when the adders are connected in series to form a ladder-like configuration, since the order of the filter is increased, the number of the adders connected in series is increased, and the operating time of additions performed in one cycle is increased. For example, for the 10th IIR filter, since 10 adders are connected in series, the operation time has to be 10 times the operation time of a single adder in one cycle. On the other hand, for the filters used in the field of image processing operations, there is a demand for high-speed operation in performing the filtering treatment of the image signal. For example, for the present TV system, operation has to be performed for each output in a time period as short as 66 ns (for one pixel cycle). Consequently, for the direct-type high-order IIR filter, it is actually impossible to obtain an IIR filter with a high order and with the ability of performing an operation for each cycle in such a short time.